Figure 2. Functional block diagram of the design
3.1 System Operation
The main part of this design is the implementation of the TMS320AV120FN, a DSP processor capable of decoding a MPEG layer-2 compressed bitstream in real-time. The bitstream is supplied to the chip via a PC parallel port using our proprietary program created for this purpose. The DSP chip then decodes the compressed bitstream producing a PCM serial output which is then converted to an analog signal by the D/A converter, TDA1305T. The functional block diagram of the design is shown below in figure 2.
3.2 Specifications
A. Software:
B. Hardware:
3.3 Theory of Operation
The TMS320AV120FN is dependant upon the parallel port to receive constant bitstream at 128 kbits/s. The parallel port was chosen because of its TTL logic and simplicity to interact with. Mike Schwankl wrote a simple C program - PIPE.EXE, shown in Appendix B which reads data from a binary MPEG encoded file and sends byte-wise each bit from the file. The program operates by reading in a byte from the file and sending it to the parallel port, where the least significant bit pin (DB-25 pin 2) is connected to the serial data input pin of the TMS320AV120FN. The TMS also requires an input data clock which is also supplied by the program. A diagram showing the parallel port pin-outs and data flow is below in figure 3.
The program then repetitively shifts the byte read-in by one bit, and sends it to then parallel port until the entire byte is sent. The data clock signal is embedded within the same loop which sends the data byte to the parallel port. The clock is synced with the data so that the data is latched on the rising edge of the clock as shown in figure 2 in Appendix C. The TMS320AV120FN has a 512 byte data buffer to withstand small variations in the incoming bitrate and can operate with bitrates lower than 448 kbits/sec. If the MPEG frame that it receives is determined invalid by the decoder algorithm then the frame will be muted and no signal will be produced.
Figure 4 shows the schematic of the complete design of the MPEG Audio Decoder Module. The compressed bitstream is brought to the TMS320AV120FN on SIN and the data is latched using the data clock ICLK. This DSP operates using a 24 MHz clock provided by the crystal oscillator connected between XTAL1 and XTAL2. The signal is decompressed using the built-in MPEG algorithm, the internal buffers and the arithmetic unit. The functional block diagram of the TMS320AV120FN is shown in figure 1 in Appendix C. The PCM output is available at the PCMOUT and also the bit clock SCLK and the left-right sample clock LRCLK. These three signals are used as an input to the DAC, Philips TDA1305T. To provide the 44.1 kHz stereo output the TMS320AV120FN also needs a stable PCM clock (PCMCLK) of 16.9344 MHz which is generated using a 33.8688 MHz crystal oscillator with a 74107 (JK flip-flop) for frequency division. This clock is also used as a system clock for the TDA1305T. There is only one possible combination of formats for both chips to communicate. The TMS320AV120FN can output a PCM with a 16-bit precision and 16-bit wordlength or 18-bit precision / 24-bit wordlength. The TDA1305T on the other hand, can input data in two different standards: the Philips standard (usually known as I2C) or the Sony standard (the LSB fixed serial format used in TMS320AV120FN). It supports 16, 18 and 20 bit precision with either 24 or 32 wordlength. All formats are shown in figure 3 in Appendix D. Considering this fact, the format used in the design is a PCM stereo bitstream with 18-bit precision and 24-bit wordlength. This is defined by driving high PCMSEL0 and PCMSEL1 on the TMS chip and CLKS1 high and CLKS2 low on the TDA1305T. The required PCM clock for this format is 384 times the sampling frequency (384*44.1 kHz=16.9344MHz), hence the frequency generated by the oscillator circuit. By setting pins OMODE0 and OMODE1 of the TMS320AV120FN to ground, the signal is defined as stereo.
The PCM data enters the TDA1305T on the pin DATA, the bit clock from SCLK to BCK and the left-right clock to pin WS of the DAC. The TDA1305T is actually a filter-DAC since it has a built-in up-sampling filter and noise shaper. The functional block diagram of this chip is shown in figure 1 in Appendix D. The output is taken from the pins VOL (left) and VOR (right). The two externally connected 1nF capacitors between VOL and FILTCL, and also VOR and FILTCR, are used for 1st order filtering so that no further post filtering is required. The analog outputs are then available through a RCA connectors and suitable for direct input to any commercially available stereo amplifiers.
