Figure 5. Oscilloscope output at the parallel port
Our design was broken up into two parts, hardware and software. The software side consisted a program called PIPE.EXE (source in Appendix B). It was written in C and compiled with Power C compiler for DOS. The hardware implementation was impossible to test individually with the resources available at Villanova. The only method available for testing the hardware component of our design was to receive the bitstream from our software side.
In testing of PIPE.EXE's ability to send the MPEG file to the decoder module, a binary file of repeating ones and zeros was used to analyze the output. The program used to make the binary file is in Appendix F. The Hewlett Packard 54504A 400 MHz digitizing oscilloscope was used to monitor the output of PIPE.EXE. In figure 6 below are the results from the testing done on the HP.
The results show the program's ability to send both the data from the file (top signal in figure 6) and the input clock signal (bottom signal). The outputs were not a constant bitrate from the parallel port because of hard disk I/O. The bitrates would fluxuate from 112 kbits/sec to 139 kbits/sec. It was uncertain if this would affect the ability of the TMS320AV120FN to decode the bitstream because of the 512 byte buffer on the TMS. The use of a multi-tasking OS like Linux
(a UNIX variant) was an alternative if the inconsistent bit-rate produced problems. The preemptive I/O scheduling of Linux OS would remedy this fluxuation. At this stage in our construction we focused on the completion of the hardware so we could begin testing of the rest of the module.
The project is currently in the phase of testing and debugging the hardware. It was necessary to produce all the required signal first in order to be able to test the functionality of the decompressor and the D/A converter. Some testing was already performed on the oscillator circuits and after verifying the functionality of the clock signals, as well as the input signals, the project is ready for its final testing phase.
