ODES-3: 3rd Workshop on Optimizations
for DSP and Embedded Systems
March 20, 2005
Hotel Valencia Santana Row,
San Jose, California
in conjunction with International Symposium on Code Generation and
Optimization (CGO)
http://www.cgo.org
PROGRAM
8:05 AM
Introduction
8:05 AM
Session 1: Compilation
-
Background data management in Subword parallelizing compilers: A test case
C. Tenllado (IMEC), P. Op de Beeck (IMEC and ESAT, Katholieke Universiteit
Leuven), M. Miranda (IMEC), G. Deconinck (ESAT, Katholieke Universiteit Leuven),
F. Catthoor (IMEC and ESAT, Katholieke Universiteit Leuven), and M. Prieto (ArTECS,
Universidad Complutense de Madrid)
-
Inter-iteration scalar replacement in the presence of conditional
control-flow
M. Budiu (Microsoft) and S. C. Goldstein (Carnegie Mellon University)
-
Compiler optimization for configurable accelerators
B. Buyukkurt, Z. Guo, and W. A. Najjar (University of California Riverside)
-
Parallelizing compilation through load-time scheduling for a superscalar
processor family
M. Hussman, M. Thies, and U. Kastens (University of Paderborn)
10:05 AM
Break
10:30 AM
Keynote
-
Applications versus Technology Driven Optimization
Nat Seshan (Texas Instruments)
11:30 PM
Lunch (on your own)1:00 PM
Session 2: Accelerators/frameworks
-
Methodology for building processor design space exploration frameworks
F. Barat, T. Vander Aa, M. Jayapala, G. Deconinck, R. Lauwereins, and H.
Corporaal (IMEC)
-
A high-level memory energy estimator based on reuse distance
T. Vander Aa, M. Jayapala, F. Barat, H. Corporaal, F. Catthoor, and G.
Deconinck (IMEC)
-
Exploiting data context switching on a VLIW coprocessor
A. Ibrahim and A. Davis (University of Utah)
-
A secure multithreaded coprocessor interface
H. Chan and I. Verbauwhede (University of California, Los Angeles)
3:00 PM
Break
3:30 PM
Session 3: Implementation strategies
-
Control flow driven code hoisting at the source code level
H. Falk (University of Dortmund)
-
16-bit floating point operations for low-end and high-end embedded processors
L. Lacassagne and D. Etiemble (CNRS and Universite Paris Sud)
-
Code and data partitioning on the Blackfin 561 dual-core platform
K. Sanghai, D. Kaeli (Northeastern University), and R. Gentile (Analog
Devices)
-
Optimized implementation of the FFT algorithm on the TMS320C62x and the TMS320C64x DSP
J. Sankaran (Texas Instruments), C. D. Cantrell, and W. J. Pervin (UT Dallas)
Program Co-chairs
Program
Committee
| Shuvra Bhattacharrya |
University of Maryland |
| Henk Corporaal |
Technical University Eindhoven |
| Alex Dean |
NC State University |
| Pradeep Dubey |
Intel Corp |
| Jose Fridman |
Analog Devices |
| Jason Fritts |
Washington University in St. Louis |
| Tor Jeremiassen |
Texas Instruments |
| Eugene John |
University of Texas at San Antonio |
| Trevor Mudge |
University of Michigan |
| Vijay Narayanan |
Penn State University |
| Ramesh Peri |
Intel Corp |
| John Reekie |
University of Technology Sydney |
| Scott Rixner |
Rice University |
Past Workshops
ODES-1:
http://www.ece.vill.edu/~deepu/odes/odes-1_program.html
ODES-2:
http://www.ece.vill.edu/~deepu/odes/odes-2_program.html