The performance requirements of digital signal processing and embedded applications are rapidly increasing, but the power and cost budgets are decreasing. Optimization plays a very important role in managing the conflicting demands. The focus of this workshop is similar to its predecessors - understand the various optimization strategies applicable to the design of DSP and embedded systems for performance, power, and cost.

Topics of interest include, but are not limited to:

• Algorithmic transformations and code/software optimization
• Hardware and software optimizations for low-power consumption and/or code density
• Coprocessor and hardware accelerators
• Compiler techniques and code generation for media processing
• Frameworks for profiling and scheduling tasks (multiple/concurrent) on various hardware resources (single-core + hardware accelerators, dual-core, system-on-a-chip, etc)
• Hardware/software tradeoffs with ASICs, FPGA's, DSPs, general-purpose processors, microcontrollers, etc as building blocks
• Retargetable compilers and reconfigurable architectures

Important dates and deadlines

• Submission: January 20, 2006
• Acceptance: February 24, 2006
• Final version: March 10, 2006

Submission guidelines

To encourage participation from both academia and industry, we are requesting submissions in either of two formats:

• A full paper, not exceeding 10 pages in length, two-column formatting preferred. It is expected that an accepted submission of this type will result in a final paper appearing in the workshop's proceedings

Include the list of authors and their affiliations, addresses, telephone and fax numbers, email addresses and the name of the corresponding author. Please send the submission/s by the deadline to: Deepu Talla via email at deepu@ti.com.