8:00 AM            Introduction

8:05 AM            Session 1: Frameworks/Accelerators

• If-conversion SSA framework for partially predicated VLIW architectures

C. Bruel (ST Microelectronics)

• Efficient architecture exploration of a clustered loop buffer

T. Vander Aa, M. Jayapala (IMEC), H. Corporaal (TU Eindhoven), F. Catthoor (IMEC), and G. Deconinck (ESAT)

• Dealing with variable trip count loops in system level exploration

M. Palkovic, F. Catthoor (IMEC), and H. Corporaal (TU Eindhoven)

• ACT: A low power VLIW cluster coprocessor for DSP applications
A. Ibrahim, A. Davis, and M. Parker (University of Utah)
• Evaluation and optimization of signal processing kernels on the TRIPS architecture

K. Bush, M. Gebhart, E. Wie, N. Yudin, B. Maher, N. Nethercote, D. Burger, and S. W. Keckler (University of Texas at Austin)

10:30 AM         Keynote

• Software Challenges in Multiprocessor Systems-on-chips
Wayne Wolf (Princeton University)

1:00 PM           Session 2: Compilation

• A temperature aware compilation for software-controller on-chip memory architecture

M. Fujita, M. Kondo, and H. Nakamura (University of Tokyo)

• Managing SPM space based on inter-application data sharing

O. Ozturk, M, Kandemir, S. W. Son (Penn State University), and I. Kolcu (University of Manchester)

• Reducing code size through storage assignment for restricted indexed addressing mode

B. Bao, C. Wu, and Z. Zhang (Chinese Academy of Sciences)

• Compiler-directed temporary array elimination

H. Koc, E. Ercanli (Syracuse University), M. Kandemir, and S. W. Son (Penn State University)

• Iterative compilation for two antagonistic objectives: Code size and performance case study
K. Heydemann (ASIM/UPMC-LIP6, France) and F. Bodin (IRISA/INRIA, France)

3:30 PM           Session 3: Implementation strategies

• Performance optimization for low-leakage caches based on sleep-line access density

R. Komiya (Fukuoka University), K. Inoue, and K. Murakami (Kyushu University)

• Parallelization strategies for network interface firmware

M. Brogioli, P. Willmann, and S. Rixner (Rice University)

• ILP-based management of multi-level memory hierarchies

O. Ozturk, M. Kandemir, and S. W. Son (Penn State University)

• Improved derivation of process networks

S. Verdoolaege, H. N. Nikolov, and T. P. Stefanov (LIACS)

Program Co-chairs

Program Committee

Shuvra Bhattacharrya	University of Maryland
Henk Corporaal	Technical University Eindhoven
Alex Dean	NC State University
Jose Fridman	Analog Devices
Jason Fritts	Saint Louis University
Tor Jeremiassen	Texas Instruments
Eugene John	University of Texas at San Antonio
Ossi Kalevo	Nokia
Edward Lee	University of California at Berkeley
Trevor Mudge	University of Michigan
Vijay Narayanan	Penn State University
Ramesh Peri	Intel
John Reekie	University of Technology Sydney
Scott Rixner	Rice University
Nat Seshan	Texas Instruments
Gary Tyson	Florida State University

Past Workshops

ODES-1: http://www.ece.vill.edu/~deepu/odes/odes-1_program.html

ODES-2: http://www.ece.vill.edu/~deepu/odes/odes-2_program.html

ODES-3: http://www.ece.vill.edu/~deepu/odes/odes-3_program.html